This invention relates generally to digital logic circuitry and, more particularly, to an improved current mode 5-bit arithmetic logic unit with parity.
Various arithmetic logic units are known in the prior art. The current mode arithmetic logic array disclosed in the above-identified U.S. Pat. No. 3,925,651 is directed to an arithmetic logic array which performs the basic arithmetic and logic functions of the present invention. The improved current mode 5-bit arithmetic logic unit with parity of the present invention provides, in addition to the basic arithmetic and logic functions, necessary and useful parity and error output signals on a 5-bit binary field. It may be used in conjunction with the above-identified Ser. No. 756,458 to perform parity prediction, parity checking, and carry error detection operations. Consequently, errors generated within the arithmetic logic unit or errors which are generated during the transmission of such binary data to the arithmetic logic unit are detected quite early in the processing operation, resulting in an overall savings of processing time.